Since the invention of integrated circuits by Dr. Jack Kilby of Texas Instruments in early years, scientists and engineers have made numerous inventions and improvements in semiconductor devices and processes. Over 50 years, the dimension of semiconductors have been significantly reduced, which translates into an increasing processing speed and decreasing power consumption. To date, the development of semiconductors has largely followed Moore's Law, which roughly states that the number of transistors in dense integrated circuits doubles about every two years. At present, semiconductor processes are developing toward below 20 nm, and some companies are embarking on 14 nm processes. Just to provide a reference herein, a silicon atom is about 0.2 nm, which means that the distance between two separate components manufactured by a 20 nm process is about only one hundred silicon atoms.
Semiconductor device manufacturing has therefore become increasingly challenging and advancing toward the physically possible limit. One of the recent developments in the semiconductor technology has been the use of silicon-on-insulators (SOI) in semiconductor manufacturing. However, the electrical characteristics of the semiconductor devices of the current silicon-on-insulator structure still need to be debugged. Therefore, there is an urgent need for a method for improving the electrical characteristics of a silicon-on-insulator MOS transistor device, as well as a silicon-on-insulator structure having better electrical characteristics.